网络研讨会:112 Gbps PAM4测试平台的关键开发步骤

演讲人:Jean-Remy Bonnefoy 数据速率不断提高,对实用SerDes通道的设计提出了越来越高的要求。在112G-PAM4上,UI只有17.86ps,PCB中的信号传输必须针对损耗、反射、串扰和电源完整性进行高度优化。本次演讲将介绍信号完整性和电源完整性设计过程,展示与测量数据相关的模拟信号完整性和电源完整性性能,以及使用112G硅晶片和高速压缩安装电缆连接器的测试板的测量眼图。由此产生的测试通道旨在满足IEEE P802.3ck-100Gb/s和OIF CEI-112G PAM4规范中对测试夹具插入损耗最严格的参考要求。

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